1. Field of the Invention
The field of the invention relates to decoupling capacitors for decoupling one part of an electrical circuit from another.
2. Description of the Prior Art
Decoupling capacitors are often used in modern powered circuits. They are used, for example, to compensate for fluctuations in the power supplied to a circuit. These fluctuations can be caused by AC signals superimposed on a DC power line or by switching in another circuit located close to the circuit in question. Decoupling capacitors are also be used to compensate for dips in the power supply due to circuits pulling load from the power supply.
Decoupling capacitors are generally arranged in parallel with the circuits that they are providing fluctuation compensation for. Arranged in this way they charge up when the power supply is high and discharge to compensate for dips when the voltage level drops.
FIG. 1a shows in circuit form and FIG. 1b in layout form a decoupling capacitor 10 used to compensate for fluctuations in power supplied to an integrated circuit or chip having a plurality of cells. This device 10 is placed in a position where one of the plurality of cells could otherwise be. The device comprises a PFET transistor 12 and an NFET transistor 14. The connectivity is such that the gate capacitance of the PFET is connected to the low power rail VSS through the channel of the NFET and the NFET gate capacitance is connected to the VDD node through the channel of the PFET. A disadvantage of this topology is that it has very poor decoupling capacitance characteristics because the channel resistance of the minimum channel length device is too large to be useful in responding to the high frequency variations in current that a fine grained decoupling capacitor must respond to. Also at the minimum channel length the density of decoupling capacitance is very low. To improve this density the channel lengths have to be increased making response time rapidly poorer. In effect, this topology is only slightly better than having no decoupling capacitor at all. Furthermore, as can be seen from the layout diagram (FIG. 1b) it is not particularly area efficient requiring a lot of empty space. This device was used for cells when the minimum distance between channels was about 90 nm.
As the size of cells within chips decreased a new decoupling capacitance was produced which was used typically in cells that had minimum channel separation of 60 nm. FIG. 2a shows a circuit diagram of such a prior art decoupling capacitance and FIG. 2b shows the layout of such a capacitance.
This provided a single FET decoupling capacitance 20, either an NFET as is shown with its gate attached to the high voltage rail VDD and its source and drain attached to the low voltage rail VSS or a PFET with its gate attached to VSS and its source and drain attached to VDD. It has the advantage of very low series resistance, but in order to achieve high capacitance densities it requires a well jog 22. That is, as it is a single, in this case n device, then a majority of the device is on the p substrate and thus, it is advantageous if this can take up most of the cell and thus the separation line between the p type substrate and the nwell is not straight but rather is bent or jogged to increase the area of the p type substrate and thus increase the area of the diffusion layers and therefore the capacitance of the device. However, these well jogs have two disadvantages. Firstly they adversely impact the adjacent cells by increasing the well proximity effect seen by those cells. Secondly the well jog requires a horizontal inset of the decoupling structure which has a significant impact on the capacitance density of the small decoupling capacitance. These small decoupling capacitances are important because there are many more opportunities to place small decoupling capacitances in standard cell arrangements than there are to place larger ones. This is because finely grained decoupling capacitances are typically placed as filler structures in blocks of standard cells where there is a free block that is not used. The minimum resistance requirement with this topology is managed by carefully controlling the number of squares of diffusion and polyresistance between the associated contacts. The contact resistance is also controlled.
Embodiments of the present invention seek to provide a decoupling capacitance with a high capacitance density that is suitable for fitting into filler spaces in standard cell blocks. Standard cells are generally formed in blocks with rows that have legal placement sites for these cells. They are quantized in placement units so that they are aligned in rows and also aligned in columns in that they are aligned to quantized placement units. Previously the quantized placement units were about 90 nm apart as this was the minimum distance between contacts. These quantized units are ever decreasing and they are now in the region of 45 nm. Standard cells are such that the boundary conditions are standard so that they can interact with each other in a standard way and thus, any standard cell can be placed in any placement site. Thus, any placement site not used can be provided with a decoupling capacitance if the decoupling capacitance is compatible with the standard cell.